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HUF76105DK8
Data Sheet January 2003
5A, 30V, 0.050 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET
This N-Channel power MOSFET is (R) manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and battery operated products. Formerly developmental type TA76105.
Features
* Logic Level Gate Drive * 5A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.050 * Temperature Compensating PSPICE(R) Model * Temperature Compensating SABER(c) Model * Thermal Impedance SPICE Model * Thermal Impedance SABER Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER HUF76105DK8 PACKAGE MS-012AA BRAND 76105DK8
Symbol
D1(8) D1(7) S1(1) G1(2)
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76105DK8T.
D2(6) D2(5) S2(3) G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5 1 2 3 4
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified HUF76105DK8 Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (R GS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 20 5 1.4 1.3 Figure 4 Figures 6, 17, 18 2.5 0.02 -55 to 150 300 260 W W/oC
oC oC oC
UNITS V V V A A A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board at 1 second. 3. 228oC/W measured using FR-4 board with 0.006 in2 of copper at 1000 seconds.
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, V GS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC
30 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 11) ID = 5A, VGS = 10V (Figures 9, 10) ID = 1.4A, VGS = 5V (Figure 9) ID = 1.3A, VGS = 4.5V (Figure 9)
1 -
0.040 0.055 0.060
3 0.050 0.072 0.078
V
THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient R JA Pad Area = 0.76 in2 (Note 2) Pad Area = 0.027 in2 (See TB377) Pad Area = 0.006 in2 (See TB377) SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 1.3A, RL = 11.5, VGS = 4.5V, RGS = 27 (Figure 15) 12 28 31 21 60 80 ns ns ns ns ns ns 50 191 228
oC/W oC/W oC/W
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8
Electrical Specifications
PARAMETER SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) 325 180 35 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID 1.4A, R L = 10.7 Ig(REF) = 1.0mA (Figure 14) 9 5.3 0.35 1.00 2.40 11 6.4 0.45 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 5A, RL = 3, VGS = 10V, RGS = 27 (Figure 16) 17 21 60 20 60 120 ns ns ns ns ns ns TA = 25oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 5A ISD = 1.4A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 1.4A, dISD/dt = 100A/s ISD = 1.4A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 39 42 UNITS V V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) ID, DRAIN CURRENT (A) 6 5 4 3 2 1 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) VGS = 4.5V, RJA = 228 oC/W
VGS = 10V, RJA = 50oC/W
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8 Typical Performance Curves
2 1 THERMAL IMPEDANCE ZJA, NORMALIZED
(Continued)
0.1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
RJA = 228oC/W
0.01 SINGLE PULSE 0.001 10-5 10 -4 10-3 10-2 10 -1 100 t , RECTANGULAR PULSE DURATION (s)
t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 101 10 2 103
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
RJA = 228oC/W
TA = 25oC FOR TEMPERATURES ABOVE 25 oC DERATE PEAK CURRENT AS FOLLOWS: I
IDM, PEAK CURRENT (A)
100
= I25
150 - TA 125
VGS = 5V 10 VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10 -4 10 -3 10 -2 10 -1 t, PULSE WIDTH (s) 10 0 10 1
10 2
103
FIGURE 4. PEAK CURRENT CAPABILITY
200 100 ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
TJ = MAX RATED TA = 25oC 100s
20 STARTING TJ = 25oC
10
10 1ms
STARTING TJ = 150oC
1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 1
10ms
VDSS(MAX) = 30V 100
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
1 0.01
If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(I AS*R)/(1.3*RATED BVDSS - VDD) +1] 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8 Typical Performance Curves
25
(Continued)
150 oC 15
ID, DRAIN CURRENT (A)
I D, DRAIN CURRENT (A)
20
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
25 -55 oC 25oC 20 VGS = 4V 15 VGS = 3.5V 10 VGS = 3V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 VGS = 10V VGS = 5V
10
5
5
0 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5
0
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
110 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 5A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 90 PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX
1.8 1.6 1.4 1.2 1.0 0.8 0.6 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 5A
70 ID = 1.4A 50
30
-80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.1
1.15 I D = 250A 1.1
1.0
1.05
0.9
1.0
0.8
0.95
0.7 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8 Typical Performance Curves
600 500 C, CAPACITANCE (pF) 400 CISS 300 COSS 200 100 0 0 5 10 15 20 25 30 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
(Continued)
10 VDD = 15V 8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 5A ID = 1.4A 0 2 4 6 Qg, GATE CHARGE (nC) 8 10
2
CRSS
0
NOTE: Refer to Farichild Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
60 VGS = 4.5V, VDD = 15V, ID = 1.3A, RL= 11.5 SWITCHING TIME (ns) 45 tr 30 tf 15 td(ON) 0 0 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 10 50 td(OFF) SWITCHING TIME (ns)
120 VGS = 10V, VDD = 15V, ID = 5A, RL= 3 90 td(OFF)
60 tr 30 td(ON) 0 0 tf 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORM
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8 Test Circuits and Waveforms
VDS RL VDD VDS VGS = 10 VGS
+
(Continued)
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Ig(REF) 0 VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
VGS
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORMS
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = -----------------------------Z JA
2. The number of copper layers and the thickness of the board 3. The use of external heat sinks 4. The use of thermal vias 5. Air flow and board orientation 6. For non-steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 23 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM.
(EQ. 1)
In using surface mount devices such as the SOP-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8
Thermal resistances corresponding to other copper areas can be obtained from Figure 23 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads.
R JA = 103.2 - 24.3 x
RJA1 = R JA2 = 159oC/W
R1 = R2 = 97oC/W
TJ1 and TJ2 define the junction temperature of the respective die. Similarly, P1 and P2 define the power dissipated in each die. The steady state junction temperature can be calculated using Equation 4 for die 1and Equation 5 for die 2. Example: Use Equation 4 to calculate TJ1 and Equation 5 to calculate TJ2 with the following conditions. Die 2 is dissipating 0.5 Watts; die 1 is dissipating 0 Watts; the ambient temperature is 70oC; the package is mounted to a top copper area of 0.1 square inches per die.
T J1 = P 1 R JA + P 2 R + T A (EQ. 4)
ln ( Area )
(EQ. 2)
300 RJA = 103.2 - 24.3 250
* ln(AREA)
228 oC/W - 0.006in2 191 oC/W - 0.027in2
R, RJA (oC/W)
200 150 100 50
TJ1 = (0 Watts)(159oC/W) + (0.5 Watts)(97oC/W) + 70oC TJ1 = 119oC
T
R = 46.4 - 21.7 * ln(AREA)
0 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) PER DIE
J2
=PR + P R + T A 2 JA 1
(EQ. 5)
TJ2 = (0.5 Watts)(159oC/W) + (0 Watts)(97oC/W) + 70oC TJ2 = 150oC The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 24 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. SPICE and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a single die, several of the new UltraFETs are offered with two die in the SOP-8 package. The dual die SOP-8 package introduces an additional thermal component, thermal coupling resistance, R. Equation 3 describes R as a function of the top copper mounting pad area.
R
= 46.4 - 21.7 x
ln ( Area )
(EQ. 3)
The thermal coupling resistance vs. copper area is also graphically depicted in Figure 23. It is important to note the thermal resistance (R JA) and thermal coupling resistance (R) are equivalent for both die. For example at 0.1 square inches of copper:
160
COPPER BOARD AREA - DESCENDING ORDER 0.020 in2 0.140 in2 0.257 in2 0.380 in2 0.493 in2
IMPEDANCE (oC/W)
120
ZJA, THERMAL
80
40
0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8 SPICE Thermal Model
REV June 1998 HUF76105DK8
th JUNCTION
Copper Area = 0.02 in2
CTHERM1 th 8 8.5e-4 CTHERM2 8 7 1.8e-3 CTHERM3 7 6 5.0e-3 CTHERM4 6 5 1.3e-2 CTHERM5 5 4 4.0e-2 CTHERM6 4 3 9.0e-2 CTHERM7 3 2 4.0e-1 CTHERM8 2 tl 1.4 RTHERM1 th 8 3.5e-2 RTHERM2 8 7 6.0e-1 RTHERM3 7 6 2 RTHERM4 6 5 8 RTHERM5 5 4 18 RTHERM6 4 3 39 RTHERM7 3 2 42 RTHERM8 2 tl 48
RTHERM1 8 CTHERM1
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
RTHERM4 5
CTHERM4
SABER Thermal Model
Copper Area = 0.02 in2
template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 8.5e-4 ctherm.ctherm2 8 7 = 1.8e-3 ctherm.ctherm3 7 6 = 5.0e-3 ctherm.ctherm4 6 5 = 1.3e-2 ctherm.ctherm5 5 4 = 4.0e-2 ctherm.ctherm6 4 3 = 9.0e-2 ctherm.ctherm7 3 2 = 4.0e-1 ctherm.ctherm8 2 tl = 1.4 rtherm.rtherm1 th 8 = 3.5e-2 rtherm.rtherm2 8 7 = 6.0e-1 rtherm.rtherm3 7 6 = 2 rtherm.rtherm4 6 5 = 8 rtherm.rtherm5 5 4 = 18 rtherm.rtherm6 4 3 = 39 rtherm.rtherm7 3 2 = 42 rtherm.rtherm8 2 tl = 48 } COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.02 in2 9.0e-2 4.0e-1 1.4 39 42 48 0.14 in2 1.3e-1 6.0e-1 2.5 26 32 35
RTHERM5 4 CTHERM5
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
CASE
TABLE 1. THERMAL MODELS 0.257 in2 1.5e-1 4.5e-1 2.2 20 31 38 0.38 in2 1.5e-1 6.5e-1 3 20 29 31 0.493 in2 1.5e-1 7.5e-1 3 20 23 25
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
HUF76105DK8 PSPICE Electrical Model
.SUBCKT HUF76105 2 1 3 ;
CA 12 8 4.95e-10 CB 15 14 5.15e-10 CIN 6 8 2.9e-10
10
REV June 1998
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 33.87 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 9.2e-10 LSOURCE 3 7 3.2e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9e-3 RGATE 9 20 3.39 RLDRAIN 2 5 10 RLGATE 1 9 9.2 RLSOURCE 3 7 3.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 22e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE CIN
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*42),6))} .MODEL DBODYMOD D (IS = 3.01e-13 IKF = 20 RS = 1.47e-2 TRS1 = -1.7e-3 TRS2 = 4e-5 CJO = 5.74e-10 TT = 2.88e-8 M = 0.43) .MODEL DBREAKMOD D (RS = 3.94e-1 TRS1 = 9.94e-4 TRS2 = 9.12e-7) .MODEL DPLCAPMOD D (CJO = 2.55e-10 IS = 1e-30 N = 10 M = 0.6) .MODEL MMEDMOD NMOS (VTO = 1.92 KP = 2.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.39) .MODEL MSTROMOD NMOS (VTO = 2.26 KP = 19 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.7 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.9 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.94e-4 TC2 = 9.84e-8) .MODEL RDRAINMOD RES (TC1 = 8e-3 TC2 = 5.3e-5) .MODEL RSLCMOD RES (TC1 = 1.e-3 TC2 = -1e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -1.87e-3 TC2 = -1.2e-6) .MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 1.7e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.2 VOFF= -2) VON = -2 VOFF= -6.2) VON = -0.5 VOFF= 0.5) VON = 0.5 VOFF= -0.5)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2003 Fairchild Semiconductor Corporation
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
HUF76105DK8 Rev. B1
HUF76105DK8 SABER Electrical Model
REV June 1998
template huf76105 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.01e-13, cjo = 5.74e-10, tt = 2.88e-8, xti = 4.5, m = 0.43) d..model dbreakmod = () d..model dplcapmod = (cjo = 2.55e-10, is = 1e-30, n = 10, m = 0.6) m..model mmedmod = (type=_n, vto = 1.92, kp = 2.1, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.26, kp = 19, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.7, kp = 0.1, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2, voff = -6.2) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5) c.ca n12 n8 = 4.95e-10 c.cb n15 n14 = 5.15e-10 c.cin n6 n8 = 2.9e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 9.2e-10 l.lsource n3 n7 = 3.2e-10 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.94e-4, tc2 = 9.84e-8 res.rdbody n71 n5 = 1.47e-2, tc1 = -1.7e-3, tc2 = 4e-5 res.rdbreak n72 n5 = 3.94e-1, tc1 = 9.94e-4, tc2 = 9.12e-7 res.rdrain n50 n16 = 9e-3, tc1 = 8e-3, tc2 = 5.3e-5 res.rgate n9 n20 = 3.39 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 9.2 res.rlsource n3 n7 = 3.2 res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 22e-3, tc1 = 1e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1.7e-6 res.rvthres n22 n8 = 1, tc1 = -1.87e-3, tc2 = -1.2e-6 spe.ebreak n11 n7 n17 n18 = 33.87 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/42))** 6)) } }
(c)2003 Fairchild Semiconductor Corporation
HUF76105DK8 Rev. B1
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PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
Rev. I2

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